`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Westlake University
// Engineer: shenziyang@westlake.edu.cn
// 
// Create Date: 2021/11/24 02:08:54
// Design Name: HW4
// Module Name: tb_clock_distribution
// Project Name: hw4
// Target Devices: VCU118
// Tool Versions: vivado 2020.1
// Description: testbench for Homework 4
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tb_clock_distribution();
    reg clk;
    reg rst_n;
    wire [5:0] F;

    initial begin
        rst_n = 1;
        #10 rst_n = 0;
    end

    always begin
        #5 clk = 1; #5 clk = 0;
    end

clock_distribution inst_clock_distribution(clk,rst_n,F);
endmodule
